https://scholars.lib.ntu.edu.tw/handle/123456789/173872
標題: | 子計畫二:時序就是一切:論電源震盪,雜訊,及溫度對時序 之影響(2/3) | 作者: | 陳中平 | 公開日期: | 31-七月-2005 | 出版社: | 臺北市:國立臺灣大學電子工程學研究所 | 摘要: | To ensure the power and signal integrity of modern VLSI circuits, it is crucial to analyze huge amount of nonlinear devices together with enormous interconnect and even sub- strate parasitics to achieve the required accuracy. Neither traditional circuit simulation engines such as SPICE nor switch-level timing analysis algorithms are equipped to han- dle such a tremendous challenge in both eciency and ac- curacy. In this paper, we establish a solid framework that simultaneously takes advantage of a novel hierarchical non- linear circuit simulation algorithm and an advanced large- scale linear circuit simulation method using a new predictor- corrector algorithm. Under solid convergence and stability guarantees, our simulator, HiSIM, a hierarchical interconnect- centric circuit simulator, is capable of handling the post- layout RLKC power and signal integrity analysis task e- ciently and accurately. Experimental results demonstrate over 180X speed up over the conventional at simulation method with SPICE-level accuracy. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/20055 | 其他識別: | 932220E002002 | Rights: | 國立臺灣大學電子工程學研究所 |
顯示於: | 電子工程學研究所 |
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932220E002002.pdf | 412.99 kB | Adobe PDF | 檢視/開啟 |
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