Design and Implementation of Power-Aware Video Codec Systems

In this dissertation, two major sources of power dissipation in video codec systems, the codec core and the frame buffer access, are covered by three research topics. For codec core, the design and implementation of power-aware flexible video codec system and power-aware MPEG-4 video encoder system are investigated in Part I and Part II respectively. As for frame buffer access, the embedded compression for frame buffer access is considered in Part III.
The importance of power-aware video codec systems are introduced in Chapter 1. The low-power design techniques to be applied in this dissertation are then reviewed in Chapter 2. Chapter 3 (of Part I) discusses the design approach for power-aware flexible video codec system, and Chapter 4 (of Part I) targets the DWT for the development of function-specific reconfigurable hardware accelerator for power-aware flexible video codec system. The design approach for power-aware MPEG-4 video encoder system is investigated in Chapter 5 (of Part II), and the designs of dominating computation-intensive tasks are described in following three chapters, including the low-power full search ME processor in Chapter 6 (of Part II), the multi-mode content-dependent low-power ME processor in Chapter 7 (of Part II), and the content-dependent low-power DCTQ processor in Chapter 8 (of Part II). Then, in Chapter 9 (of Part III), the low-complexity multi-mode embedded compression engine is considered for frame buffer access. The principal contributions and future directions are concluded in Chapter 10. Finally, an appendix about the survey of advances in hardware architectures for image and video coding is given in Chapter 11.