https://scholars.lib.ntu.edu.tw/handle/123456789/289911
標題: | Automatic router for the pin grid array package | 作者: | Chen, S.-S. Chen, J.-J. Tsai, C.-C. SAO-JIE CHEN |
公開日期: | 2000 | 卷: | 146 | 期: | 6 | 起(迄)頁: | 275-281 | 來源出版物: | IEE Proceedings: Computers and Digital Techniques | 摘要: | A pin grid array (PGA) package router is described. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment, topological routing and geometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router has a user-friendly graphic interface and can be applied practically to industrial strength VLSI packaging. © lEE, 1999. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-0033346494&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/289911 |
ISSN: | 13502387 | DOI: | 10.1049/ip-cdt:19990797 | SDG/關鍵字: | Boundary conditions; Electronics packaging; Graphical user interfaces; Integrated circuit testing; Interconnection networks; Routers; Substrates; Pin grid array (PGA) packages; Integrated circuit layout |
顯示於: | 電機工程學系 |
檔案 | 描述 | 大小 | 格式 | |
---|---|---|---|---|
00838804.pdf | 807.79 kB | Adobe PDF | 檢視/開啟 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。