DC Field | Value | Language |
dc.contributor | Dept. of Electr. Eng., National Taiwan Univ. | en |
dc.contributor.author | Chen, S.-S. | en_US |
dc.contributor.author | Chen, J.-J. | en_US |
dc.contributor.author | Tsai, C.-C. | en_US |
dc.contributor.author | SAO-JIE CHEN | - |
dc.creator | Chen, S.-S.;Chen, J.-J.;Tsai, C.-C.;Chen, S.-J. | - |
dc.date.accessioned | 2018-09-10T03:29:31Z | - |
dc.date.available | 2018-09-10T03:29:31Z | - |
dc.date.issued | 2000 | - |
dc.identifier.issn | 13502387 | - |
dc.identifier.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-0033346494&partnerID=MN8TOARS | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/289911 | - |
dc.description.abstract | A pin grid array (PGA) package router is described. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment, topological routing and geometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router has a user-friendly graphic interface and can be applied practically to industrial strength VLSI packaging. © lEE, 1999. | - |
dc.format | application/pdf | en |
dc.format.extent | 827176 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en | en |
dc.relation | Computers and Digital Techniques, IEE Proceedings- | en |
dc.relation.ispartof | IEE Proceedings: Computers and Digital Techniques | en_US |
dc.source | AH-Scopus to ORCID | - |
dc.subject.other | Boundary conditions; Electronics packaging; Graphical user interfaces; Integrated circuit testing; Interconnection networks; Routers; Substrates; Pin grid array (PGA) packages; Integrated circuit layout | - |
dc.title | Automatic router for the pin grid array package | - |
dc.type | conference paper | en |
dc.identifier.doi | 10.1049/ip-cdt:19990797 | - |
dc.identifier.scopus | 2-s2.0-0033346494 | - |
dc.relation.pages | 275-281 | - |
dc.relation.journalvolume | 146 | - |
dc.relation.journalissue | 6 | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.openairetype | conference paper | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
item.fulltext | with fulltext | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.orcid | 0000-0003-1152-171X | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
Appears in Collections: | 電機工程學系
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