DC 欄位 | 值 | 語言 |
dc.contributor | Dept. of Electr. Eng., National Taiwan Univ. | en |
dc.contributor.author | Chang, Hao-Chieh | en_US |
dc.contributor.author | Yang, Zhong-Lan | en_US |
dc.contributor.author | Lian, Chung-Jr | en_US |
dc.contributor.author | LIANG-GEE CHEN | en_US |
dc.creator | Chang, Hao-Chieh;Yang, Zhong-Lan;Lian, Chung-Jr;Chen, Liang-Gee | - |
dc.date.accessioned | 2018-09-10T03:43:43Z | - |
dc.date.available | 2018-09-10T03:43:43Z | - |
dc.date.issued | 2001 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0035023720&doi=10.1109%2fISCAS.2001.921040&partnerID=40&md5=ba4ff37272c4614e20daf3afb45baa31 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/292082 | - |
dc.description.abstract | This paper presents a hardware-efficient architecture of tree-depth scanning (TDS) and multiple-quantization (MQ) scheme for MPEC-4 still texture coding. By means of the novel architecture, the TDS can achieve its maximal throughput to area ratio and minimal external memory access with only one wavelet-tree size on-chip memory. Besides, MQ adopts the proposed POT (power of 2) quantization, which is proved to have very similar performance to generic (user-defined coefficients) scalar quantization, to achieve the most cost-effective hardware implementation. The prototyping chip has been implemented in a TSMC 0.35 /spl mu/m CMOS technology. This architecture can handle 30 4-CIF frames per second with 5 spatial layers and 3 SNR layers scalability at 100 MHz clock frequency. © 2001 IEEE. | - |
dc.format | application/pdf | en |
dc.format.extent | 424331 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en | en |
dc.relation | Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on | en |
dc.relation.ispartof | ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings | - |
dc.source | AH | - |
dc.subject.other | Architecture designs; External memory access; Frames per seconds; Hardware implementations; Maximal throughput; Multiple quantizations; Novel architecture; Scalar quantization; CMOS integrated circuits; Forestry; Motion Picture Experts Group standards; Image compression; Microprocessor chips; Scanning; Signal to noise ratio; Software prototyping; Vector quantization; Hardware; Image coding; Multiple quantization (MQ); Tree depth scanning (TDS) | - |
dc.title | Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding | - |
dc.type | conference paper | en |
dc.relation.conference | 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 | - |
dc.identifier.doi | 10.1109/ISCAS.2001.921040 | - |
dc.identifier.scopus | 2-s2.0-0035023720 | - |
dc.relation.pages | 193 - 196 | - |
dc.relation.journalvolume | 2 | - |
item.openairetype | conference paper | - |
item.fulltext | with fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.orcid | 0000-0001-9746-9355 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系
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