A 0.8V 0.77mW at 50MHz 128Kb Four-Way Set-Associative 2-Level CMOS Cache Memory Using Two-Stage WLOTC/BLOTC Tag-Compare Scheme and Sense Wordline/Bitlines (SWL/SBL) Tag Sense Amps with an 8-T Tag Cell in Level 2 and a 10-T Shrunk Logic Swing (SLS) Memory