Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model

Please use this identifier to cite or link to this item: https://scholars.lib.ntu.edu.tw/handle/123456789/294328

Title:	Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model
Authors:	J. B. Kuo S. C. Lin JAMES-B KUO
Issue Date:	Oct-2001
Start page/Pages:	891-894
Source:	International Conference on Semiconductor IC Technology (ICSICT)
URI:	http://scholars.lib.ntu.edu.tw/handle/123456789/294328
DOI:	10.1109/icsict.2001.982038
Appears in Collections:	電機工程學系

Show full item record

Last Week
0

Last month

checked on Sep 12, 2020

checked on Oct 20, 2020

Check

DSpace CRIS