Low-voltage analog tripler circuit
Journal
Journal of Analog Integrated Circuits and Signal Processing
Journal Volume
26
Journal Issue
2
Pages
125-128
Date Issued
2001-02
Author(s)
Abstract
A new low-voltage CMOS tripler is presented in this paper. It is realized by the square-law characteristics of MOS transistors operating in saturation. The proposed circuit has been fabricated in a 0.8 μm CMOS process. Experimental results have been given to demonstrate the feasibility of the proposed circuit. It is expected to be useful in low-voltage analog signal-processing applications.
SDGs
Type
journal article