https://scholars.lib.ntu.edu.tw/handle/123456789/294599
Title: | A bipartition-codec architecture to reduce power in pipelined circuits | Authors: | Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai, FEI-PEI LAI |
Issue Date: | Feb-2001 | Journal Volume: | 20 | Journal Issue: | 2 | Start page/Pages: | 343-348 | Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/294599 | DOI: | 10.1109/43.908477 |
Appears in Collections: | 生醫電子與資訊學研究所 |
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