Performance-driven placement for dynamically reconfigurable FPGAs
Resource
ACM Transactions on Design Automation of Electronic Systems 7 (4): 628-642
Journal
ACM Transactions on Design Automation of Electronic Systems
Journal Volume
7
Journal Issue
4
Pages
628-642
Date Issued
2002
Author(s)
Abstract
In this article, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2, 27.0, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.
SDGs
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
11.pdf
Size
216.25 KB
Format
Adobe PDF
Checksum
(MD5):3fddd96f80f41fec4470dd22b0e8c03d