https://scholars.lib.ntu.edu.tw/handle/123456789/301450
標題: | An efficient embedded bitstream parsing processor for MPEG-4 video decoding system | 作者: | Chang, Y.-C. Huang, C.-C. Chao, W.-M. LIANG-GEE CHEN |
公開日期: | 2003 | 卷: | 2003-January | 起(迄)頁: | 168-171 | 來源出版物: | International Symposium on VLSI Technology, Systems, and Applications, Proceedings | 會議論文: | 20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003 | 摘要: | In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5. © 2003 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-20744456842&doi=10.1109%2fVTSA.2003.1252579&partnerID=40&md5=b80dfed1def6cd95ff44517bd2e6e4a7 http://scholars.lib.ntu.edu.tw/handle/123456789/301450 |
ISSN: | 19308868 | DOI: | 10.1109/VTSA.2003.1252579 | SDG/關鍵字: | Decoding; Motion Picture Experts Group standards; Video signal processing; Advanced Simple Profile; Bitstream parsing; Bitstream parsing processors; DCT coefficients; Instruction set; MPEG-4 video; Processor architectures; Video standard; Binary sequences |
顯示於: | 電機工程學系 |
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