Concurrent Error-Detectable Butterfly Chip for Real-Time FFT Processing Through Time Redundancy

This paper presents a chip design of a fast Fourier transform (FFT) butterfly module with a novel concurrent error detection (CED) technique. It is a time-redundant realization based on the direct complex computation approach. By symmetric and exchanging designing strategy, the recomputation step can be performed by interleaving the real part and imaginary part circuits in a complex function. It leads to less hardware overhead of about 7/(4n + 8) where n is the word length, and the capability of error detection is still as robust as the duplicated module technique. The CED butterfly is designed with 1.2-μm CMOS technology by using the structural silicon compiler. Theoretical analysis and experimental results are presented. It is shown that this design is very attractive in the real-time high-reliability DSP system. Its regular structure reveals that the proposed algorithm and architecture are easy to implement on VLSI or WSI. © 1993 IEEE.