https://scholars.lib.ntu.edu.tw/handle/123456789/303242
標題: | Tile-based power planning during floorplanning | 作者: | Fang, J.P. SAO-JIE CHEN |
關鍵字: | Bismuth; Circuits; Clocks; Energy consumption; Piecewise linear approximation; Power engineering and energy; Power generation; Temperature; Tiles; Very large scale integration | 公開日期: | 2003 | 起(迄)頁: | 195-198 | 來源出版物: | IEEE International SOC Conference, SOCC 2003 | 摘要: | In this paper, we introduce a tile-based approach to power planning at the stage of floorplanning. For a given floorplan solution, an associated tile graph of power density is generated, and the temperature of the floorplan is evaluated tile by tile. In contrast to the direct evaluation from the power consumption of circuit blocks and neglecting the effect of heat diffusion, we take the effect of heat diffusion in a die into consideration. Also, we simplify the computing of temperature by way of a tile graph, which make the heat estimation and thus the power planning in the floorplanning stage possible. © 2003 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-84945414757&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/303242 |
DOI: | 10.1109/SOC.2003.1241491 | SDG/關鍵字: | Bismuth; Clocks; Energy utilization; Networks (circuits); Power generation; Temperature; Tile; VLSI circuits; Circuit blocks; Direct evaluations; Floor-planning; Heat diffusions; Piecewise linear approximations; Power densities; Power engineering and energies; Power planning; Piecewise linear techniques |
顯示於: | 電機工程學系 |
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