https://scholars.lib.ntu.edu.tw/handle/123456789/304377
標題: | 3-Dimensional Vertical Parallel Plate Capacitors in an SOI CMOS Technology for Integrated RF Circuits | 作者: | Kim, Jonghae Plouchart, Jean-Olivier Zamdmer, Noah Sherony, Melanie LIANG-HUNG LU Tan, Yue Yoon, Meeyoung Jenkins, Keith A. Kumar, Mähender Ray, Asit Wagner, Lawrence |
關鍵字: | CMOS; RF Circuits; SOI; VPP | 公開日期: | 六月-2003 | 起(迄)頁: | 29-32 | 來源出版物: | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 會議論文: | 2003 Symposium on VLSI Circuits | 摘要: | This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 urn SOI CMOS technology. An effective capacitance density of 1.76 fF/μm2 is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/304377 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0141761455&partnerID=40&md5=7ab15a85dfde34498a4a1537111bc15a |
DOI: | 10.1109/vlsic.2003.1221153 | SDG/關鍵字: | Capacitance; Capacitors; Electric resistance; Q factor measurement; Silicon on insulator technology; Skin effect; Radiofrequency (RF) integrated circuits; CMOS integrated circuits |
顯示於: | 電子工程學研究所 |
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