A high-precision time-to-digital converter using a two-level conversion scheme
Resource
IEEE Transactions on Nuclear Science 51 (4): 1349-1352
Journal
IEEE Transactions on Nuclear Science
Journal Volume
51
Journal Issue
4 I
Pages
1349-1352
Date Issued
2004
Author(s)
Abstract
This paper describes a design of time-to-digital converter (TDC) using a two-level conversion scheme. The first level is accomplished by a multi-phase sampling technique with the aid of delay-locked loop (DLL). Then the input signal and its adjacent sampling clock are manipulated and sent into a vernier delay line (VDL) sampling circuit at the second level. The proposed TDC can provide high resolution with less hardware compared to one level VDL sampling circuit with the same dynamic range. A new architecture of dual DLL circuit is also implemented to stabilize delay control against process and ambient variations. A test chip is designed and fabricated in 0.35-μm logic technology. With an input reference clock within 130 to 160 MHz, the TDC achieves 24 to 30 ps resolution. The DNL is less than ±0.55 LSB and INL is within + 1 to - 1.5 LSB.
Subjects
Delay-locked loop; Time-to-digital converter (TDC); Vernier delay line
SDGs
Other Subjects
Delay-locked loops; Loop filters; Time-to-digital convertor (TDC); Vernier delay line (VDL); Computer simulation; Control nonlinearities; Control system analysis; Design aids; Graph theory; Information analysis; Mathematical models; Signal processing; Time and motion study; Voltage measurement; Analog to digital conversion
Type
journal article
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