https://scholars.lib.ntu.edu.tw/handle/123456789/309229
標題: | Simultaneous routing and buffering in SOC floorplan design | 作者: | Fang, J.P. Tong, Y.-S. SAO-JIE CHEN |
公開日期: | 2004 | 卷: | 151 | 期: | 1 | 起(迄)頁: | 17-22 | 來源出版物: | IEE Proceedings: Computers and Digital Techniques | 摘要: | An EDA tool to deal with the problems of routing and buffer-insertion in system-on-chip floorplanning simultaneously is developed. This routing and buffering tool mainly consists of a Manhattan routing (MR) algorithm and a maze-based between-buffer routing algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-1542581484&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/309229 |
ISSN: | 13502387 | DOI: | 10.1049/ip-cdt:20040072 | SDG/關鍵字: | Congestion constraints; Cost functions; Manhattan routing (MR); Algorithms; Approximation theory; Estimation; Graph theory; Matrix algebra; Optimization; Perturbation techniques; Problem solving; Routers; Topology; VLSI circuits |
顯示於: | 電機工程學系 |
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