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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
A Temporal Assertion Extension to Verilog
Details
A Temporal Assertion Extension to Verilog
Journal
2nd International Symposium on Automated Technology for Verification and Analysis(ATVA04)
Pages
499-504
Date Issued
2004-10
Author(s)
K. H. Chang
W. T. Tu
Y. J. Yeh
SY-YEN KUO
DOI
10.1007/978-3-540-30476-0_45
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/310569
Type
conference paper