https://scholars.lib.ntu.edu.tw/handle/123456789/310569| Title: | A Temporal Assertion Extension to Verilog | Authors: | K. H. Chang W. T. Tu Y. J. Yeh S. Y. Kuo SY-YEN KUO |
Issue Date: | Oct-2004 | Start page/Pages: | 499-504 | Source: | Proceedings of the 2nd International Symposium on Automated Technology for Verification and Analysis(ATVA04) | URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/310569 | DOI: | 10.1007/978-3-540-30476-0_45 |
| Appears in Collections: | 電機工程學系 |
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