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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Techniques to Reduce Synchronization in Distributed Parallel Logic Simulation
Details
Techniques to Reduce Synchronization in Distributed Parallel Logic Simulation
Journal
16th IASTED International Conference on Parallel and Distributed Computing and Systems(PDCS'04)
Pages
404-409
Date Issued
2004-11
Author(s)
K. H. Chang
W. T. Tu
H. W. Wang
Y. J. Yeh
SY-YEN KUO
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/310572
Type
conference paper