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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
A Design for Testability Technique for Low Power Delay Fault Testing
Details
A Design for Testability Technique for Low Power Delay Fault Testing
Journal
IEICE Transactions on Electronics
Journal Volume
E87-C
Journal Issue
4
Pages
621-628
Date Issued
2004-04
Author(s)
CHIEN-MO LI
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/310815
Type
journal article
