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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Multilevel full-chip routing with testability and yield enhancement
Details
Multilevel full-chip routing with testability and yield enhancement
Journal
International Workshop on System Level Interconnect Prediction, SLIP
Pages
29-36
Date Issued
2005
Author(s)
Li, K.S.-M.
Lee, C.-L.
Chang, Y.-W.
Su, C.
Chen, J.-E.
YAO-WEN CHANG
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-30944441475&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/316483
Type
conference paper