A high-speed scalable shift-register based on-chip serial communication design for SoC applications
Resource
Research in Microelectronics and Electronics, 2005 PhD
Journal
2005 PhD Research in Microelectronics and Electronics
Journal Volume
I
Pages
67-70
Date Issued
2005
Author(s)
Abstract
In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design (Kimura et al., 2003).
SDGs
Type
conference paper
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