https://scholars.lib.ntu.edu.tw/handle/123456789/317636
標題: | 0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems | 作者: | T. Y. Chiang JAMES-B KUO |
公開日期: | 四月-2005 | 卷: | 152 | 期: | 2 | 起(迄)頁: | 123-126 | 來源出版物: | IEE Proceddings on Circuits, Devices and Systems | 摘要: | The authors report a 0.7 V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7 V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time compared to the conventional Manchester carry look-ahead circuit based on two-dimensional device simulation MEDICI results. © IEE, 2005. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-20444448936&doi=10.1049%2fip-cds%3a20041138&partnerID=40&md5=ff0b71243a1b9dd8c999e9fbaf45c7a5 | DOI: | 10.1049/ip-cds:20041138 | SDG/關鍵字: | CMOS integrated circuits; Electric network analysis; Leakage currents; Logic circuits; Silicon on insulator technology; Threshold voltage; Transistors; Arithmetic circuits; Asymmetrical dynamic threshold pass-transistors (ADTPT); Dynamic threshold pass-transistors (DTPT); Partially depleted (PD) SOI CMOS; VLSI circuits |
顯示於: | 電機工程學系 |
檔案 | 描述 | 大小 | 格式 | |
---|---|---|---|---|
01436117.pdf | 859.44 kB | Adobe PDF | 檢視/開啟 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。