0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems
Resource
IEE Proceedings Circuits, Devices and Systems, 152(2), 123-126
Journal
IEE Proceddings on Circuits, Devices and Systems
Journal Volume
152
Journal Issue
2
Pages
123-126
Date Issued
2005-04
Author(s)
T. Y. Chiang
Abstract
The authors report a 0.7 V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7 V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time compared to the conventional Manchester carry look-ahead circuit based on two-dimensional device simulation MEDICI results. © IEE, 2005.
Other Subjects
CMOS integrated circuits; Electric network analysis; Leakage currents; Logic circuits; Silicon on insulator technology; Threshold voltage; Transistors; Arithmetic circuits; Asymmetrical dynamic threshold pass-transistors (ADTPT); Dynamic threshold pass-transistors (DTPT); Partially depleted (PD) SOI CMOS; VLSI circuits
Type
journal article
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