https://scholars.lib.ntu.edu.tw/handle/123456789/318024
標題: | A DLL-Based Frequency Multiplier For MBOA-UWB System | 作者: | K-J Hsiao TAI-CHENG LEE |
關鍵字: | Delay-locked loops; Frequency multiplier; UWB | 公開日期: | 六月-2005 | 起(迄)頁: | 42-45 | 來源出版物: | IEEE Symposium on VLSI Circuits | 摘要: | A delay-locked loop (DLL)-based frequency multiplier is designed for the ultrawideband (UWB) Mode-1 system. This clock generator with 528-MHz input reference frequency can achieve less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. The UWB clock generator has been fabricated in a 0.18-)-μm CMOS process and consumes only 54 mW from a 1.8-V supply while exhibiting a sideband magnitude of -35.3 dB and -94 dBc/Hz phase noise at the frequency offset of 50 kHz. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/318024 | DOI: | 10.1109/VLSIC.2005.1469329 | SDG/關鍵字: | CMOS integrated circuits; Delay circuits; Frequency synthesizers; Spurious signal noise; Delay locked loops; Frequency multipliers; Sideband magnitude; UWB; Broadband networks |
顯示於: | 電子工程學研究所 |
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