https://scholars.lib.ntu.edu.tw/handle/123456789/321262
標題: | A 32-bit logarithmic number system processor | 作者: | Huang, S.-C. LIANG-GEE CHEN Chen, T.-H. |
公開日期: | 1996 | 卷: | 14 | 期: | 3 | 起(迄)頁: | 311-319 | 來源出版物: | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology | 摘要: | To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log 2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The basic concept behind DP is that variable x can be divided into two parts in bit representation to be implemented. Thus, ROM or PLA table can be reduced to a reasonable size and this will make a high precision design allowable. The basic idea of IDLA is that the function 20.x can be obtained approximately through iterative linear approximations. By this method, only adder, shifter and a small PLA are required, unlike the previous designs which require ROM and multiplier. The experiment results reveal that the proposed design is more attractive than the previous researches in the LNS processor. © 1996 Kluwer Academic Publishers. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0030399262&doi=10.1007%2fBF00929624&partnerID=40&md5=d818b8f16adb3c8246a36d69f30dfa15 http://scholars.lib.ntu.edu.tw/handle/123456789/321262 |
ISSN: | 09225773 | DOI: | 10.1007/BF00929624 | SDG/關鍵字: | Adders; Approximation theory; Design; Iterative methods; ROM; Shift registers; Logarithmic number system; Program processors |
顯示於: | 電機工程學系 |
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