https://scholars.lib.ntu.edu.tw/handle/123456789/324048
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, W.-P. | en_US |
dc.contributor.author | Liu, H.-Y. | en_US |
dc.contributor.author | Chang, Y.-W. | en_US |
dc.contributor.author | YAO-WEN CHANG | zz |
dc.creator | Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W. | - |
dc.date.accessioned | 2018-09-10T05:58:31Z | - |
dc.date.available | 2018-09-10T05:58:31Z | - |
dc.date.issued | 2006 | - |
dc.identifier.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-43349099463&partnerID=MN8TOARS | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/324048 | - |
dc.description.abstract | Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction. The underlying idea behind MSV is the trade-off between power saving and performance. In this paper, we present an effective voltage assignment technique based on dynamic programming. Given a netlist without reconvergent fanouts, the dynamic programming can guarantee an optimal solution for the voltage assignment. We then generate a level shifter for each net that connects two blocks in different voltage domains, and perform power-network aware floorplanning for the MSV design. Experimental results show that our floorplanner is very effective in optimizing power consumption under timing constraints. Copyright 2006 ACM. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE/ACM International Conference on Computer-Aided Design | - |
dc.source | AH-Scopus to ORCID | - |
dc.subject.classification | [SDGs]SDG7 | - |
dc.subject.other | Design; Dynamic programming; Electric power utilization; Integrated circuit layout; Integrated circuits; Mathematical programming; Optimization; Systems engineering; Time measurement; Timing circuits; chip designs; Computer-aided design; Effective voltage; Experimental results; Floor-planning; Floorplanner; international conferences; level shifters; Multiple supply voltages; Net list; Optimal solutions; Power consumption (CE); Power consumption reduction; Power savings; Timing constraints; Timing optimization; Voltage assignments; voltage domains; voltage islands; Energy conservation | - |
dc.title | Voltage Island aware floorplanning for power and timing optimization | - |
dc.type | conference paper | en |
dc.identifier.doi | 10.1109/ICCAD.2006.320063 | - |
dc.identifier.scopus | 2-s2.0-43349099463 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
dc.relation.pages | 389-394 | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.openairetype | conference paper | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Information and Electronics Technologies | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-0564-5719 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電子工程學研究所 |
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