https://scholars.lib.ntu.edu.tw/handle/123456789/325752
標題: | A period tracking based on-chip sinusoidal jitter extraction technique | 作者: | C.-Y. Kuo JIUN-LANG HUANG |
關鍵字: | Built-in self-diagnosis; Built-in self-test; Jitter decomposition; Sinusoidal jitter | 公開日期: | 四月-2006 | 卷: | 2006 | 起(迄)頁: | 400 - 405 | 來源出版物: | Proceedings of the IEEE VLSI Test Symposium | 會議論文: | 24th IEEE VLSI Test Symposium | 摘要: | In this paper, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal's cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations. © 2006 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33751104775&doi=10.1109%2fVTS.2006.10&partnerID=40&md5=bb7b172b6d2de067ff6d6d873b628d3a | DOI: | 10.1109/VTS.2006.10 | SDG/關鍵字: | Built-in self test; Computer simulation; Digital signal processing; Electric delay lines; Jitter; Built-in self-diagnosis; Jitter decomposition; Sinusoidal jitter; Chip scale packages |
顯示於: | 電子工程學研究所 |
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01617624.pdf | 452.45 kB | Adobe PDF | 檢視/開啟 |
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