https://scholars.lib.ntu.edu.tw/handle/123456789/332572
標題: | A clock-fault tolerant architecture and circuit for reliable nanoelectronics system | 作者: | AN-YEU(ANDY) WU Ang, W.T. Rao, H.F. Yu, C. Liu, J. Wey, I.-C. Wu, A.-Y. Zhao, H. Chen, J. AN-YEU(ANDY) WU |
公開日期: | 2007 | 起(迄)頁: | 186-191 | 來源出版物: | 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 | URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-48349141207&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/332572 |
DOI: | 10.1109/DTIS.2007.4449516 |
顯示於: | 電機工程學系 |
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