https://scholars.lib.ntu.edu.tw/handle/123456789/341005
標題: | Energy-saving techniques for low-power graphics procrssing unit | 作者: | Chang, C.-M. Chien, S.-Y. Tsao, Y.-M. Sun, C.-H. Lok, K.-H. Cheng, Y.-J. SHAO-YI CHIEN |
關鍵字: | Adaptive multi-thread; Component; Configurable memory array; Frequency scaling; Low power GPU; Stream processor; Unified shader | 公開日期: | 2008 | 卷: | 1 | 來源出版物: | 2008 International SoC Design Conference, ISOCC 2008 | 摘要: | This paper presents a graphics processing unit with energy-saving techniques. Several techniques and architectures are proposed to achieve high performance with low power consumption. First of all, low power core pipeline is designed with 2-issue VLIW architecture to reduce power consumption while achieving the processing capability of 400MFLOPS or 800MOPS. In addition, inter/intra adaptive multi-threading scheme can increase the performance by increasing hardware utilization, and the proposed configurable memory array architecture can reduce off-chip memory accessing frequency by caching both input data and output results. Furthermore, for graphics applications, a geometry-content-aware technique called early-rejection-after-transformation is proposed to remove redundant operations for invisible triangles. As for circuit level power reduction, power-aware frequency scaling is proposed to further reduce the power consumption. ©2008 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-69949104513&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/341005 |
DOI: | 10.1109/SOCDC.2008.4815617 | SDG/關鍵字: | Computer graphics; Computer graphics equipment; Dynamic frequency scaling; Electric power utilization; Energy conservation; Graphics processing unit; Image coding; Memory architecture; Pipeline processing systems; Program processors; Programmable logic controllers; Component; Frequency-scaling; Low Power; Memory array; Multi-thread; Stream processor; Unified shader; Very long instruction word architecture |
顯示於: | 電子工程學研究所 |
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