Fewest vias design for microstrip guard trace by using overlying dielectric

Journal

IEEE 17th Topical Meeting on Electrical Performance of Electronic Packaging

Pages

321-324

Date Issued

2008-10

Author(s)

Y.-S. Cheng

W.-D. Guo

G.-H.Shiue

H.-H. Cheng

C.-C. Wang

DOI

10.1109/EPEP.2008.4675945

URI

http://scholars.lib.ntu.edu.tw/handle/123456789/342491

Type

conference paper