https://scholars.lib.ntu.edu.tw/handle/123456789/342647
標題: | A 50.8-53-GHz clock generator using a harmonic-locked PD in 0.13-μm CMOS | 作者: | Chihun Lee Lan-Chou Cho Jia-Hao Wu SHEN-IUAN LIU |
關鍵字: | Clock generator; Phase detector; Rference spur; Voltage-controlled oscillator (VCO) | 公開日期: | 五月-2008 | 卷: | 55 | 期: | 5 | 起(迄)頁: | 404-408 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-μm process. The measured reference spur is - 59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm × 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply. © 2008 IEEE. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/342647 https://www.scopus.com/inward/record.uri?eid=2-s2.0-44949100225&doi=10.1109%2fTCSII.2007.914430&partnerID=40&md5=4ca660372f6494b9f05ae6f82c03e84e |
ISSN: | 15497747 | DOI: | 10.1109/tcsii.2007.914430 | SDG/關鍵字: | Circuit oscillations; Clocks; Harmonic generation; Variable frequency oscillators; Clock generator; On-chip loop filter; Quadruplicate-harmonic-locked phase detector (PD); Voltage-controlled oscillator; CMOS integrated circuits |
顯示於: | 電機工程學系 |
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