A digitally calibrated 64.3-66.2GHz phase-locked loop
Journal
The 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
Pages
307-310
Date Issued
2008-06
Author(s)
Abstract
In this paper, a 64.3–66.2GHz digitally calibrated phase-locked loop (PLL) is presented in 0.13μm CMOS technology. A digital calibration circuit is adopted to align the center operation frequency between the VCO and the divider. At 64.3GHz, the measured phase noise at 1MHz offset is 84.1dBc/Hz. The PLL consumes 72mW without output buffers from 1.2V supply.
SDGs
Type
conference paper