Power integrity chip-package-PCB co-Simulation for I/O interface of DDR3 high-speed memory

Journal

Elect. Design Adv. Packag. Systems Symp.

Pages

31-34

Date Issued

2008-12

Author(s)

H.-H. Chuang

S.-J. Wu

M.-Z. Hong

D. Hsu

R. Huang

DOI

10.1109/EDAPS.2008.4735991

URI

http://scholars.lib.ntu.edu.tw/handle/123456789/342781

Type

conference paper