Power integrity chip-package-PCB co-Simulation for I/O interface of DDR3 high-speed memory
Journal
Elect. Design Adv. Packag. Systems Symp.
Pages
31-34
Date Issued
2008-12
Author(s)
Abstract
The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS co-simulation of chip-package-PCB is important for the DDR3 circuit design.
SDGs
Type
conference paper