The effect of gate recess profile on device performance of Ga/sub 0.51/In/sub 0.49/P/In/sub 0.2/Ga/sub 0.8/As doped-channel FET's
Journal
IEEE Transactions on Electron Devices
Journal Volume
46
Journal Issue
1
Pages
48-54
Date Issued
1999
Author(s)
Abstract
The effect of gate recess profile on device performance of Ga0.51In0.4gP/In0.2Gao.sAs doped-channel FET's was studied. In the experiment, Ga0.51In0.4gP/In0.2Gao.sAs dopedchannel FET's (DCFET's) using triple-recessed gate structure were compared with devices using single-recessed and doublerecessed gate structures. It is found that triple-recessed gate approach provides higher breakdown voltage (35 V) than singlerecessed (16 V) and double-recessed gate (28 V) approaches. This is attributed to the larger aspect ratio in the triple-recessed gate structure. A unified method to calculate the breakdown voltages of MESFET's, HEMT's and DCFET's (or MISFET's) of any given arbitrary recessed gate profile was proposed and used to explain the experimental results. © 1999 IEEE.
Type
journal article