A design of 1T memory cells using channel traps for long data retention time
Journal
2009 International Semiconductor Device Research Symposium
Date Issued
2009
Author(s)
Chen, Y.-T.
Huang, C.-F.
Sun, H.-C.
Wu, T.-Y.
Ku, C.-Y.
Liu, C.W.
Hsu, Y.-C.
Chen, J.-S.
Abstract
This paper proposes a design of IT memory cells that utilizes the modulation of drain current by channel traps and offers these advantages: 1. capacitorless structure, 2. long data retention time, 3. excellent endurance characteristics, 4. low power consumption, 5. 3D integration compatibility.
SDGs
Type
conference paper