Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique

Journal

Power and Timing Optimization Symposium

Date Issued

2009-09

Author(s)

C. H. Lin

J. B. Kuo

URI

http://scholars.lib.ntu.edu.tw/handle/123456789/351956

Type

conference paper