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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique
Details
Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique
Journal
Power and Timing Optimization Symposium
Date Issued
2009-09
Author(s)
C. H. Lin
J. B. Kuo
JAMES-B KUO
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/351956
Type
conference paper