Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs
Resource
IEEE Transactions on Circuits and Systems I: Regular Papers, 56(5), 877-885
Journal
IEEE Transactions on Circuits and Systems-I
Journal Volume
56
Pages
877-885
Date Issued
2009-05
Author(s)
Abstract
This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (δΣ) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz δΣ fractional-N PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18-μm CMOS process. The fully-integrated δΣ fractional-N PLL dissipates 22 mW from a 1.8-V supply voltage. © 2009 IEEE.
SDGs
Type
journal article