https://scholars.lib.ntu.edu.tw/handle/123456789/358075
標題: | DyML: Dynamic Multi-Level flow control for Networks on Chip | 作者: | Tsai, W.-C. Lan, Y.-C. Chen, S.-J. Hu, Y.-H. SAO-JIE CHEN |
公開日期: | 2010 | 起(迄)頁: | 429-434 | 來源出版物: | IEEE International SOC Conference, SOCC 2010 | 摘要: | A novel hybrid Dynamic Multi-Level (DyML) flow control scheme for Networks-on-Chip is proposed. DyML uses a buffer fluidity flow monitor for real-time monitoring the incoming traffic volume. Instead of buffering as many flits as a router can afford, DyML dynamically adjusts the proper number of buffering flits. Accordingly, DyML causes less in-transit packets in the network, thus improves packet latency and mitigates traffic congestion. Experiments indicated that DyML averagely improves the latency performance of a state-of-the-art routing algorithm (Odd-Even) by 25.43% in synthetic traffics and by 0.90% in real traffics. © 2010 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-79960730444&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/358075 |
DOI: | 10.1109/SOCC.2010.5784670 | SDG/關鍵字: | Control schemes; Hybrid dynamics; Incoming traffic; Latency performance; Multi-level; Networks on chips; Packet latencies; Real time monitoring; Real traffic; Flow control; Microprocessor chips; Programmable logic controllers; Traffic congestion |
顯示於: | 電機工程學系 |
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