A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm

Journal

IEEE Transactions on Circuits and Systems II: Express Briefs

Journal Volume

57

Journal Issue

6

Pages

430-434

Date Issued

2010

Author(s)

AN-YEU(ANDY) WU

Wu, C.-T.

Shen, W.-C.

Wang, W.

AN-YEU(ANDY) WU

DOI

10.1109/TCSII.2010.2048358

URI

http://www.scopus.com/inward/record.url?eid=2-s2.0-77953727164&partnerID=MN8TOARS

http://scholars.lib.ntu.edu.tw/handle/123456789/358395

Type

journal article