A parameterized SPICE macromodel of resistive random access memory and circuit demonstration
Journal
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Pages
163-166
Date Issued
2011
Author(s)
Abstract
A parameterized SPICE macromodel of resistive random access memory (RRAM) is demonstrated to simulate the memory chip. The two-terminal RRAM model has the features of (1) initial condition settings of high resistance state (HRS) or low resistance state (LRS) (2) a forming behavior option (3) DC/transient mode selection (4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation. The features have been verified in the simulation of memory peripheral circuits with good convergence.
Type
conference paper