https://scholars.lib.ntu.edu.tw/handle/123456789/365394
標題: | Parallel architecture core (PAC)-the first multicore application processor SoC in Taiwan part II: Application programming | 作者: | AN-YEU(ANDY) WU Chen, J.-M. Liu, C.-N. Yang, J.-K. Tseng, S.-Y. Shih, W.-K. AN-YEU(ANDY) WU |
關鍵字: | Dual-core architecture; Dynamic voltage/frequency scaling (DVFS); Heterogeneous multicore; PAC; PACDSP; Power-aware; VLIW DSP | 公開日期: | 2011 | 卷: | 62 | 期: | 3 | 起(迄)頁: | 383-402 | 來源出版物: | Journal of Signal Processing Systems | 摘要: | Two representative multimedia applications-AAC and H.264/AVC decoders on the parallel architecture core (PAC) SoC are introduced in the second part of the two introductory papers. The applications have been programmed on the PACDSP core and the PAC SoC to demonstrate the high-performance, low-power DSP computations and the effectiveness of the dynamic voltage and frequency scaling (DVFS) capability on the heterogeneous multicore SoC. First, techniques to exploit data- and instruction-level parallelisms existing in the application kernels are described for performance optimizations on the clustered VLIW architecture of PACDSP with the distributed register organization. Next, two variation techniques of asymmetric programming model are introduced by examples of decoders. Then, the energy efficiency of the programmable multimedia SoC is demonstrated using an innovative power-aware H.264/AVC decoder. Finally, a DVFS-aware framework for soft real-time video playback is provided by extending the power-aware decoding scheme. The work provides practical references of realizing multimedia applications on PAC SoC suitable for rich-function and resource constraint portable devices. © 2010 Springer Science+Business Media, LLC. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-79954621223&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/365394 |
DOI: | 10.1007/s11265-010-0471-z | SDG/關鍵字: | Dual-core architecture; Dynamic voltage/frequency scaling (DVFS); Heterogeneous multicore; PAC; PACDSP; Power-aware; VLIW DSP; Architecture; Decoding; Embedded systems; Energy efficiency; Knowledge based systems; Motion Picture Experts Group standards; Multimedia systems; Parallel architectures; Parallel programming; Very long instruction word architecture; Multicore programming |
顯示於: | 電機工程學系 |
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