https://scholars.lib.ntu.edu.tw/handle/123456789/366443
標題: | A 1~16Gb/s wide-range clock/data recovery circuit with bidirectional frequency detector | 作者: | Chang-Lin Hsieh SHEN-IUAN LIU |
關鍵字: | Clock and data recovery (CDR); frequency detector (FD); quadrature divider; voltage-controlled oscillator (VCO); wide-range | 公開日期: | 八月-2011 | 卷: | 58 | 期: | 8 | 起(迄)頁: | 487-491 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A 1-16-Gb/s wide-range clock and data recovery (CDR) circuit is presented by using the proposed bidirectional frequency detector. This CDR circuit is fabricated in 0.13-μm CMOS technology, and its active area is 0.134 mm 2 without a loop filter. The power consumption of this CDR circuit is 160 mW for a supply of 1.5 V. A modified interpolation voltage-controlled oscillator is presented, which covers from 4.9 to 10.2 GHz. A quadrature divider is used to generate accurate quadrature clocks. © 2011 IEEE. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/366443 https://www.scopus.com/inward/record.uri?eid=2-s2.0-80051781038&doi=10.1109%2fTCSII.2011.2158719&partnerID=40&md5=f151f0f8e15fcd35ee36e0f8d09a3229 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2011.2158719 | SDG/關鍵字: | Circuit oscillations; Clocks; Oscillistors; Recovery; Timing circuits; Variable frequency oscillators; Voltage dividers; Active area; Clock and data recovery; CMOS technology; Frequency detectors; Loop filter; Quadrature clocks; quadrature divider; wide-range; Clock and data recovery circuits (CDR circuits) |
顯示於: | 電機工程學系 |
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