3D simulation of substrate noise coupling from Through Silicon Via (TSV) and noise isolation methods
Journal
2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Pages
181-184
Date Issued
2012
Author(s)
Abstract
This paper presents simulation results of substrate noise coupling between through silicon via (TSV) and MOSFET. Electrical noise coupling through coexistence of junction capacitances and threshold modulation in substrate is studied and discussed through 2D and 3D transient analyses in this paper. Furthermore, noise isolation methods including guard rings and grounded shield TSV are incorporated to improve the noise decoupling and are examined to verify their effectiveness.
Type
conference paper