A low-power low-latency processor for real-time on-line local mean decomposition
Journal
2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Pages
205-208
Date Issued
2015
Author(s)
Hsueh, H.-C.
Abstract
In this work, a first time realization of an on-line LMD processor is proposed. The processor chip is implemented with the core area of 2.33mm 2 using TSMC 90-nm process with high-Vt cell. Operating at 20MHz, the chip consumes 2.28mw from a 1.0V supply voltage. Confirmed by post-layout simulation, after the initial latency of 0.833 seconds, the proposed processor is able to produce decomposed ECG data of 5 product functions and a residue in short burst every 277.8ms with computational latency 4.9ms. The accuracy of the hardware design is validated through decomposing real ECG data obtained from MIT-BIH arrhythmia database. The performance shows that the proposed on-line LMD processor is well suited to low-power, real-time wearable biomedical applications.
SDGs
Type
conference paper