A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving

This paper presents an energy-recycling micro-architecture and the associated adiabatic logic for ultra-low energy applications, such as implantable bioelectronics. The proposed design achieves low power by transferring and recycling energy between digital logic blocks along with the signal propagation. The CMOS-like layout methodology allows the adiabatic logic core to be synthesized and auto-placed-and-routed with current EDA tools for complex digital systems. A 50% energy saving can be achieved for up to 100 MHz compared to conventional static CMOS logic. As a proof of concept, a 14-tap 8-bit finite impulse response (FIR) filter has been implemented in 90-nm CMOS for implantable neural signal processing. With only 16% area overhead compared to the static CMOS counterpart, the proposed design achieves 70% to 53% of energy reduction for 87 kHz to 410 kHz from a 1 V supply. The FIR filter realized with the proposed energy-recycling logic achieves an FoM of 5.33 nW/MHz/Tap/In-bit/Coeff-bit, yielding a 1.9× to 42× higher energy efficiency than the state-of-the-art custom energy-efficient FIR designs. © 2016 IEEE.