https://scholars.lib.ntu.edu.tw/handle/123456789/404568
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | M. H.Liao | en_US |
dc.contributor.author | C.-H. Yeh | en_US |
dc.contributor.author | C.-C. Lee | en_US |
dc.contributor.author | C.-P. Wang | en_US |
dc.creator | C.-P. Wang;C.-C. Lee;C.-H. Yeh;M. H.Liao | - |
dc.date.accessioned | 2019-03-11T08:02:19Z | - |
dc.date.available | 2019-03-11T08:02:19Z | - |
dc.date.issued | 2016 | - |
dc.identifier.issn | 21583226 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/404568 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84963545390&doi=10.1063%2f1.4945346&partnerID=40&md5=8511508603238da27b2c72348830e488 | - |
dc.description.abstract | The vertical gate-all-around (V-GAA) Si nano-tube (NT) devices with different diameter dimensions are studied in this work with the promising device performance. The V-GAA structure makes the transistor easy to be scaled down continuously to meet the complementary metal-oxide-semiconductor (CMOS) scaling requirements of the 7/10 nm technology node and beyond. The Si NT device with the hollow structure is demonstrated to have the capability to "deplete" and "screen-out" the out-of gate control carriers in the center of the NT and further result in the better device short channel control. Based on the study in this work, the V-GAA Si NT device with the optimized diameter dimension (=20 nm) can benefit the Ion-state current and reduce the Ioff-state stand-by power simultaneously, due to the less surface roughness scattering and the better short channel control characteristics. The proposed V-GAA Si NT device is regarded as one of the most promising candidates for the future application of the sub-7/10 nm logic era. © 2016 Author(s). | - |
dc.relation.ispartof | AIP Advances | en_US |
dc.subject.other | Field effect transistors; Gallium alloys; Metals; MOS devices; Nanotubes; Oxide semiconductors; Reconfigurable hardware; Surface roughness; Transistors; Complementary metal oxide semiconductors; Device performance; Dimension effects; Future applications; Hollow structure; Short-channel controls; Surface roughness scattering; Technology nodes; Silicon | - |
dc.title | The investigation of the diameter dimension effect on the Si nano-tube transistors | en_US |
dc.type | journal article | en |
dc.identifier.scopus | 2-s2.0-84963545390 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
dc.relation.pages | 35021 | - |
dc.relation.journalvolume | 6 | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.openairetype | journal article | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
crisitem.author.orcid | 0000-0003-2942-4520 | - |
顯示於: | 電機工程學系 |
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