https://scholars.lib.ntu.edu.tw/handle/123456789/484471
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hwang, R.-Y. | en_US |
dc.contributor.author | Lai, F. | en_US |
dc.contributor.author | FEI-PEI LAI | zz |
dc.creator | Hwang, R.-Y.;Lai, F. | - |
dc.date.accessioned | 2020-04-16T02:35:13Z | - |
dc.date.available | 2020-04-16T02:35:13Z | - |
dc.date.issued | 1994 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/484471 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0028547574&doi=10.1049%2fip-cdt%3a19941519&partnerID=40&md5=9c1e6b504cbb341cd197bbff6e2c6541 | - |
dc.description.abstract | Exploiting loop parallelism is an important way to enhance system performance. For loop-carried dependence, the original DO loop is converted into a DOACROSS loop to function concurrently. In general, synchronization operations are inserted to maintain order dependence during parallel execution. For each processor in a shared memory multiprocessor, if the executing sequence is the same as the original source program, the action of synchronization operation is correct; however, if each processor is used out of order, such as in the superscalar machine, the action of synchronization operation may be incorrect. The synchronization marker insertion method proposed resolves this problem in two steps: (i) proper synchronization markers are appended into the array element of dependences, and (ii) synchronization markers are generated during intermediate code generation. Finally, algorithms are proposed to prevent error during instruction scheduling. | - |
dc.relation.ispartof | IEE Proceedings: Computers and Digital Techniques | - |
dc.subject.other | Algorithms; Error analysis; Multiprocessing systems; Program compilers; Synchronization; Systems analysis; Data dependence; Guiding instruction scheduling; Shared memory multiprocessor; Superscalar based multiprocessor; Synchronization markers; Data handling | - |
dc.title | Guiding instruction scheduling with synchronization markers on a superscalar based multiprocessor | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.1049/ip-cdt:19941519 | - |
dc.identifier.scopus | 2-s2.0-0028547574 | - |
dc.relation.pages | 398-404 | - |
dc.relation.journalvolume | 141 | - |
dc.relation.journalissue | 6 | - |
item.openairetype | journal article | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Biomedical Electronics and Bioinformatics | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.orcid | 0000-0003-0179-7325 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 生醫電子與資訊學研究所 |
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