https://scholars.lib.ntu.edu.tw/handle/123456789/497778
Title: | Logic Synthesis in a Nutshell | Authors: | Jiang, J.H. Devadas, S. JIE-HONG JIANG |
Issue Date: | 2009 | Start page/Pages: | 299-404 | Source: | Electronic Design Automation | URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/497778 | DOI: | 10.1016/B978-0-12-374364-0.50013-8 |
Appears in Collections: | 電機工程學系 |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.