https://scholars.lib.ntu.edu.tw/handle/123456789/497928
標題: | WiT: Optimal wiring topology for electromigration avoidance | 作者: | Chang, H.-Y. Chang, C.-L. HUI-RU JIANG |
關鍵字: | Algorithms; electromigration (EM); global routing; integrated circuit reliability; linear programming | 公開日期: | 2012 | 卷: | 20 | 期: | 4 | 起(迄)頁: | 581-592 | 來源出版物: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 摘要: | Due to excessive current densities, electromigration (EM) may trigger a permanent open- or short-circuit failure in signal wires or power networks in analog or mixed-signal circuits. As the feature size keeps shrinking, this effect becomes a key reliability concern. Hence, in this paper, we focus on wiring topology generation for avoiding EM at the routing stage. Prior works tended towards heuristics; on the contrary, we first claim this problem belongs to class P instead of class NP-hard. Our breakthrough is, via the proof of the greedy-choice property, we successfully model this problem on a multi-source multi-sink flow network and then solve it by a strongly polynomial time algorithm. Experimental results prove the effectiveness and efficiency of our algorithm. © 2006 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84859003368&doi=10.1109%2fTVLSI.2011.2116049&partnerID=40&md5=acac2345dc699ba0fa0f896ce2393b8d | DOI: | 10.1109/TVLSI.2011.2116049 |
顯示於: | 電機工程學系 |
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