https://scholars.lib.ntu.edu.tw/handle/123456789/498212
標題: | A 10-Gb/s Inductorless CMOS Limiting Amplifier with Third-Order Interleaving Active Feedback | 作者: | Huang, Huei-Yan JUN-CHAU CHIEN LIANG-HUNG LU |
關鍵字: | Active feedback; Bandwidth enhancement techniques; Broadband amplifiers; Gain flatness; Inductive peaking; Limiting amplifiers; Optical communications | 公開日期: | 2007 | 卷: | 42 | 期: | 5 | 起(迄)頁: | 1111-1120 | 來源出版物: | IEEE Journal of Solid-State Circuits | 摘要: | This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-μm CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 231 -1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10 -12 are 300 and 10 mVPP, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68 × 0.8 mm2 where the active circuit area only occupies 0.32 × 0.6 mm2. © 2007 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/498212 https://www.scopus.com/inward/record.uri?eid=2-s2.0-34247333794&doi=10.1109%2fJSSC.2007.894819&partnerID=40&md5=04580d048cd7c2d95f10761e15de6623 |
ISSN: | 0018-9200 | DOI: | 10.1109/JSSC.2007.894819 | SDG/關鍵字: | Active feedback; Chip size; Inductive peaking; Input sensitivity; Bandwidth; Bit error rate; CMOS integrated circuits; Electric potential; Feedback; Gain control; Optical communication; Broadband amplifiers |
顯示於: | 電機工程學系 |
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