https://scholars.lib.ntu.edu.tw/handle/123456789/498492
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, Tai-Cheng | en_US |
dc.contributor.author | Li, Yih-Lang | en_US |
dc.contributor.author | TAI-CHENG LEE | zz |
dc.creator | Lee, Tai-Cheng;Li, Yih-Lang | - |
dc.date.accessioned | 2020-06-11T06:21:01Z | - |
dc.date.available | 2020-06-11T06:21:01Z | - |
dc.date.issued | 2019 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/498492 | - |
dc.relation.ispartof | IEEE Trans. VLSI Syst. | - |
dc.title | Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TVLSI.2019.2915254 | - |
dc.identifier.url | https://doi.org/10.1109/TVLSI.2019.2915254 | - |
dc.relation.pages | 2434-2446 | - |
dc.relation.journalvolume | 27 | - |
dc.relation.journalissue | 10 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
item.openairetype | journal article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電機工程學系 |
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